Succesful Seminconductor Fabless

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Du 8 au 10 novembre 2011Paris
Technology and supply chain challenges for fabless semiconductor companies
Fabless semiconductor companies constantly face the challenge of designing competitive products which can easily be manufactured by their manufacturing partners with good yields. Comprehensive access for their design, test and quality engineers to the design rules and guidelines is key to implement the required design for manufacturability (DfM) practices.

Preliminary Program :

-  Novembre 8th

-  Novembre 9th
  • 9.00 AM - Session 1 : Industrialization
    How to make semiconductor industrialization supply chain easier for fabless companies ?
    Today all the Semiconductor fabless companies have the same issues to ensure Time to Market or Time to volume. There are more and more suppliers to manage with different background : Wafer Fab, Test House, Packaging, FA Lab. This situation could be problematic when you need to optimize cost & time in order to be competitive on your market and answer your customer needs. Knowing that the product life is shorter, the good management of this situation became a success key factor. Major players will share their experience during this session.

  • 1.00 PM – Networking lunch

  • 2.00 PM - Session 2 : Design
    First time right designs are not only increasingly key to optimize time to market and development costs, but they also set to integrate an increasing number of parameters upfront way beyond the classical IC design of the sole “silicon crystals”. Packaging and testability require particular attention during the design phase so as to best use available or new technologies for low cost manufacturing. It is therefore a key challenge for fabless semiconductor companies to integrate these technologies and their suppliers into their design flows.

  • 7.30 PM - Business Reception

-  November 10th
  • 9.00 AM - Session 3 – Packaging
    Never have semiconductor packaging technologies changed so radically and fast as they have been doing in the past years. Packaging accounts for a rising share of the mean IC build of material and IC packaging follows a fast moving trend to wafer level packaging and 3D integration. It is key for fabless semiconductor companies to understand and take part in this evolution so as to draw benefits for their products and influence this trend. When can the expected cost and performance levels be met with design optimizations and when is the use of new package platforms needed ? How to make the right package and supplier choice ? Examples and “field rules” will be given by semiconductor fabless.

  • 1.00 PM – Networking Lunch

  • 2.00 PM – End of SSF 2011

Registration : dowload aplication form

Contacts :
Benjamin CROUILLERE
Serma Techynologies
Sales Engineer / Ingénieur Commercial

Sandrine LEROY
Yole Developpement
Media & PR Manager

Crédits © JESSICA FRANCE 2005 - 2016
Le programme CAP’TRONIC est financé par le Ministère de l’Economie et des Finances.